法国专利FR3021806A1 METHOD FOR PROGRAMMING NONVOLATILE MEMORY CELL COMPRISING A SHARED SELECTION TRANSISTOR GRID

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专利摘要:
The invention relates to a method for controlling two twin memory cells (C11, C12) each comprising a floating gate transistor (FGT11, FGT12) comprising a state control gate (CG), in series with a selection transistor ( ST11, ST12) comprising a selection control gate (SGC) common to the two memory cells, the drains of the floating gate transistors being connected to the same bit line (BL), the method comprising programming steps of the first cell memory (C11, C21) by injecting hot electrons, applying a positive voltage (BLV3) to the bit line and a positive voltage (Vpg) to the state control gate of the first memory cell, and simultaneously, applying to the state control grid of the second memory cell a positive voltage (Vsp) capable of passing a programming current (I2) in the second memory cell (C12, C22), without passing it in one programmed state.
公开号:FR3021806A1
申请号:FR1454839
申请日:2014-05-28
公开日:2015-12-04
发明作者:Rosa Francesco La；Stephan Niel；Arnaud Regnier
申请人:STMicroelectronics SA；
IPC主号:

专利说明:

[0001] The present invention relates to electrically erasable Programmable Read-Only Memory (EEPROM) electrically erasable and electrically erasable type non-volatile memories. The present invention more particularly relates to a non-volatile memory, comprising memory cells each comprising a floating gate transistor and a selection transistor gate shared with an adjacent memory cell called "twin". FIG. 1 is the electrical diagram of memory cells C11, C12 of the aforementioned type, belonging to two adjacent pages Pi, Pi + 1 of a memory plane. The memory cells C11, C12 are accessible for reading and writing via a bit line BL, a word line WL <i, i + 1> and grid control lines CGL , CGL Each memory cell comprises a floating gate transistor, respectively FGT11, FGT12 The control gate CG of the transistor FGT11 is connected to the gate control line CGL via The control gate CG of the transistor FGT12 is connected to the gate control line CGL via a contact C4 The drain regions of the transistors FGT11, FGT12 are connected to a contact C4. a bit line BL via contacts C1 The vertical gate SGC is connected to a word line WL <i, i + 1> common to the two memory cells via a contact C3. floating gate FGT11, FGT12 also has its source terminal connected to a source line SL via a tr selection hististor ST11, ST12 respectively. The selection transistors ST11, ST12 share the same selection control gate SGC. The two memory cells C11, C12 are called "binoculars" because they share the same selection control gate SGC and the same bit line BL. The channel regions CH1, CH2 of the transistors FGT11, FGT12, ST11, ST12 are at the electric potential of the box PW, as represented by dashed lines. Finally, the source regions of the transistors ST11, ST12 are electrically connected to the source line SL.
[0002] This can be connected via a contact C5 to a general source line made in a metal level. Each common control gate SGC is preferably a vertical grid buried in a substrate receiving the memory plane, the line 5 of source SL being also a buried line. The common SGC control grids, or selection grids of twin memory cells, are connected to the word line WL <i, i + 1>. Such memory cells are erased or programmed by the channel, that is to say by carrying the substrate at a positive erasing or negative programming voltage causing the extraction of electrical charges from their floating gates or the injection electric charges in their floating gates, by Fowler-Nordheim effect. More particularly, erasure of a memory cell is ensured by combining the positive voltage applied to the substrate with a negative voltage applied to the control gate CG of its floating gate transistor, while the control gate of the gate transistor The floating cell of the twin memory cell receives a positive erase inhibit voltage to prevent it being simultaneously erased. Likewise, the programming of a memory cell is ensured by combining a negative voltage applied to the bit line BL and the substrate PW to a positive voltage applied to the control gate CG of its floating gate transistor, while the The gate of the floating gate transistor of the twin memory cell receives a negative programming inhibit voltage to prevent it from being simultaneously programmed. Finally, the reading of a memory cell is ensured by applying a positive voltage to the control gate of its floating gate transistor, as well as a positive voltage to the corresponding bit line, while the twin memory cell, which is connected to the same bit line, receives on its control gate a negative reading inhibition voltage to prevent it being simultaneously read. This memory plane structure having twin memory cells comprising a shared vertical selection grid and buried in the substrate, has the advantage of being of small size.
[0003] This conventional memory plane and memory cell structure also requires the provision of a word line decoder capable of applying a positive read voltage to a memory cell to be read, while applying a negative read inhibition voltage. to its twin memory cell, as was recalled above. It may therefore be desirable to simplify the line decoder. It may also be desired to optimize the reading and programming operations of the memory cells, particularly in terms of power consumption.
[0004] Embodiments are directed to a method for controlling a non-volatile memory on a semiconductor substrate, comprising: at least one bit line, at least two gate control lines, at least one word line, at least one pair of twin memory cells, having a first memory cell comprising a first floating gate transistor having a control gate connected to a first gate control line, a first conduction terminal connected to the bit line and a second gate terminal. conduction connected to a source line via a first selection transistor having a selection control gate connected to the word line, and a second memory cell having a second floating gate transistor having a control gate connected to the second gate control line, a first conduction terminal connected to the bit line and a second connected conduction terminal the source line via a second select transistor sharing with the first selection transistor selecting control gate. According to one embodiment, the method comprises steps of: programming the first memory cell by injecting hot electrons, via a programming current passing through the first memory cell, applying a first positive voltage to the bit line and a second positive voltage at the first gate control line, and during programming of the first memory cell, applying to the second gate control line a third positive voltage capable of passing a programming current. in the second memory cell, without passing the second memory cell into a programmed state. According to one embodiment, the third voltage is selected so as to provide soft programming of the second memory cell so that the second memory cell can not have a negative threshold voltage regardless of its programmed or erased state. . According to one embodiment, the method comprises steps of reading a memory cell of the pair of memory cells, comprising: applying a positive reading voltage to the control gate of the floating gate transistor of the memory cell in front of be read, and apply zero voltage to the control gate of the floating gate transistor of the twin memory cell. According to one embodiment, the method comprises an erasure step of simultaneously applying an erase voltage to the control gates of the floating gate transistors of the first and second memory cells. According to one embodiment, the programming operation of the first memory cell comprises steps of verifying the depleted state of the pair of memory cells, and of performing a programming of the first memory cell and a first memory cell. soft programming of the second memory cell as long as one or the other of the first and second memory cells is in the depleted state, followed by steps of checking the programmed state of the first memory cell, and programming the first memory cell as long as it is not in the programmed state. Embodiments also include a non-volatile memory on a semiconductor substrate, comprising: at least one bit line, at least two gate control lines, at least one word line, at least one pair of twin memory cells , comprising a first memory cell comprising a first floating gate transistor having a control gate connected to a first gate control line, a first conduction terminal connected to the bit line, and a second conduction terminal connected to a gate line. source via a first selection transistor having a selection control gate connected to the word line, and a second memory cell having a second floating gate transistor having a control gate connected to the second line of gate control, a first conduction terminal connected to the bit line and a second conduction terminal connected to the stern line e via a second selection transistor sharing with the first selection transistor the selection control gate, and means for programming the first memory cell independently of the second memory cell and vice versa. According to one embodiment, the memory is configured to: program the first memory cell by injecting hot electrons, through a programming current passing through the first memory cell, applying a first positive voltage to the line bit and a second positive voltage at the first gate control line, and during the programming of the first memory cell, apply to the second gate control line 10 a third positive voltage adapted to pass a programming current in the gate. second memory cell, without passing the second memory cell in a programmed state. According to one embodiment, the third voltage is selected so as to provide soft programming of the second memory cell so that the second memory cell can not have a negative threshold voltage regardless of its programmed or erased state. According to one embodiment, the memory comprises a word line decoder connected to the word line and to the gate control lines, the decoder being configured for, during the reading of a memory cell of the pair of memory cells binoculars, apply a positive read voltage to the control gate of the floating gate transistor of the memory cell to be read, and apply a zero voltage to the control gate of the floating gate transistor of the twin memory cell. According to one embodiment, the selection control gate is a buried vertical gate having for the first selection transistor a vertical channel region extending opposite a first face of the buried vertical control gate, and for the second selection transistor a vertical channel region which extends opposite a second face of the buried vertical control gate, and opposite the channel region of the first selection transistor. According to one embodiment, the memory cells of the pair of twin memory cells share a single selection transistor. According to one embodiment, the pair of memory cells comprises: a first doped region extending along a first upper edge of the buried gate, forming a drain region of the selection transistor and a source region of the floating gate transistor, a first memory cell of the pair of memory cells, a second doped region extending along a second upper edge of the buried gate opposite the first upper edge, forming a drain region of the Selection transistor and a source region of the floating gate transistor, a second memory cell of the pair of memory cells, and a third doped region extending along two opposite lower edges of the buried gate, forming a common source region of the selection transistor of the first memory cell and the selection transistor of the second memory cell, each the pair of memory cells having a vertical channel region extending from a respective side of the buried gate, between the first or second doped region and the third doped region. According to one embodiment, the memory comprises a word line decoder connected to the word line and to the gate control lines, the decoder being configured for, during the erasing of memory cells, applying an erase voltage simultaneously with the first and second grid control lines. According to one embodiment, the memory is configured for, during the programming operation of the first memory cell: checking the depleted state of the pair of memory cells, and programming the first memory cell and simultaneously applying soft programming to the second memory cell, as long as one or the other of the first and second memory cells is in the depleted state, and check the programmed state of the first memory cell, and program the first memory cell as long as that it is not in the programmed state. According to one embodiment, the memory comprises a row of pairs of twin memory cells connected to the word line and the gate control lines, the memory being configured to program a word formed by a plurality of memory cells in the row connected to each other. to one of the two grid control lines, and during programming of the word: perform a read operation of the row of pairs of twin memory cells and storage of the words read, perform an operation of erasure of the row of twin memory cell pairs read, perform word programming of the memory cells of the row of 7 memory cell pairs, including programming of the first memory cell of the memory cell pairs of the array, according to the words stored and possibly word to write, and simultaneously perform a soft programming of second memory cells of the 5 pre programmed memory cells, and perform a second operation of programming the second memory cell of the memory cell pairs of the row, according to the stored words and possibly the word to be written, and simultaneously perform a soft programming of the first memory cells of the 10 seconds programmed memory cells. Embodiments of the invention will be described in the following, in a nonlimiting manner in relation to the appended figures among which: FIG. 1 previously described, is an electrical diagram of the memory cells of FIG. 1, FIG. is a schematic sectional view of a pair of twin memory cells sharing a common vertical grid of selection transistors, Fig. 3 is a schematic sectional view of the memory cell pair of Fig. 1, illustrating a programming method. 4 is a schematic sectional view of the pair of memory cells of FIG. 1, illustrating a method of reading a memory cell, FIG. 5 is a schematic sectional view of the pair of memory cells. of memory cells of Figure 2, illustrating a method of programming a memory cell, according to one embodiment, Figure 6 is a schematic sectional view of the pair of cells 2, illustrating a method of reading a memory cell, according to one embodiment, FIG. 7 is a schematic sectional view of the pair of memory cells of FIG. 2, illustrating an erasing method. of the pair of memory cells, according to one embodiment, FIG. 8 represents distribution curves of the number of memory cells of a memory, respectively at different states, as a function of the threshold voltage of the gate transistor. FIG. 9 schematically represents circuits of a memory plane in which the programming method can be implemented, according to one embodiment, FIG. 10 represents steps executed during the programming of a cell. memory, Figure 11 is a circuit diagram of a pair of memory cells sharing a same selection transistor.
[0005] Figure 2 is a schematic sectional view of two twin memory cells C11, C12, having a selection transistor vertical gate SGC common to both memory cells. The memory cells C11, C12 are formed on a PW substrate of conductivity type P. The substrate is formed in a semiconductor plate called "wafer" WF. The PW box is isolated from the rest of the wafer WF by an N-doped N-insulation layer which surrounds the entire box. Each memory cell C11, C12 comprises a floating gate transistor FGT11, FGT12 and a selection transistor ST11, ST12. Each floating gate transistor FGT11, FGT12 comprises a drain region n1, a source region 20 n2, a floating gate FG, a state control gate CG, and a channel region CH1 extending under the floating gate FG between the drain regions n1 and source n2. The vertical selection gate SGC is buried in the substrate PW and isolated from the latter via an insulating layer D3, for example oxide SiO2, forming the gate oxide of the selection transistors ST11, ST12. Region n2 extends along an upper edge of the buried vertical grid SGC. The gate SGC reaches a source region n3 common to the transistors ST11, ST12, in contact with the NISO layer, which thus forms a source line SL of the transistors S11, ST12. Region n3 extends along two lower edges of the vertical grid SGC. Each selection transistor ST11, ST12 thus comprises a drain region common to the source region n2 of the floating gate transistor FGT11, FGT12 of its cell, the common source region n3, and a channel region CH2 extending vertically on the along the SGC grid between the n2 drain and n3 source regions. Note that region n3 can be omitted if the SGC grid reaches the NISO layer.
[0006] Regions n1, n2, n3 are generally formed by N-doping of the PW substrate. The floating gates FG are generally made of polycrystalline silicon of level 1, or "polyl", and are formed on the substrate PW by means of a tunnel oxide layer D1. The state control gates 5CG are generally made of polycrystalline silicon of level 2, or "poly2". Each state control gate CG is formed on one of the floating gates FG previously covered with an oxide layer D2. The SGC grid is formed in a trench filled with level 0 polycrystalline silicon, or "poly0", isolated from the substrate by the oxide layer D3. According to the manufacturing method adopted, the conducting trench forming the SGC grid may have no electrical discontinuity. It can then be used directly as word line WL. The two memory cells C11, C12 are covered by a dielectric insulating material D0, which may also be SiO2 oxide.
[0007] The drain regions n1 of the transistors FGT11, FGT12 are connected to the same bit line BL via a contact C1 passing through the insulator DO. Table PG1 in Appendix 1 describes with reference to FIG. 3 voltage values applied to the memory cells during programming of the memory cell C11. The column "Ref." describes the reference assigned to each voltage value and the column "Ex." describes examples of voltage values. "GND" is the mass potential, namely the potential of the wafer WF, generally 0 V. During the hot electron programming of the memory cell C11, the two transistors FGT11, 25 ST11 cooperate for the purpose of injecting charges. in the floating gate FG. The selection transistor ST11 has a conductive channel CH2 in which a current 11 (represented by arrows in FIG. 3) is formed comprising electrons with high kinetic energy, called "hot electrons". When the current reaches the conducting channel CH1 of the floating gate transistor FGT11, an injection zone is formed in which certain high energy electrons are injected into the floating gate FG under the effect of a transverse electric field created by the voltage applied to the CG control grid. The transfer of charges from the substrate PW to the floating gate FG (programming) is thus carried out via the selection transistor ST11, and by applying a high potential difference (here 10 V) to the floating gate, allowing this charge transfer. It can be noted that in the twin cell C12, a current 12 (represented by arrows in FIG. 3) also flows in the CH1 channel of the transistor FGT12 and in the CH2 channel of the transistor ST12. Current 12 is insufficient to program cell C12 because the control gate CG of transistor FGT12 receives insufficient voltage (GND) to form an electric field capable of injecting electrons into the floating gate FG of this transistor. The presence of the current 12, not negligible, therefore leads to unnecessary power consumption.
[0008] Table ER1 in Appendix 1 provides voltage values applied to the memory cells when erasing the memory cell C11. The erasure is performed without passing through the selection transistor ST11 which remains blocked, by applying a high electric field (here 10 V) between the source and the floating gate FG of the memory cell to be erased. Thus, the electrons are extracted from the floating gate by Fowler-Nordheim tunnel effect. The erasure of the twin memory cell C12 is prevented by applying to the control gate of the transistor FGT12 a non-erasing voltage Vner (for example 2.5 V). Erasing of memory cells is usually done per page of memory cells. However, all the memory cells of a page do not have identical erasure threshold voltages, particularly because of gate oxide thickness variations from one memory cell to another. As a result, the memory cells do not fade at the same speed, and some memory cells are in an "over-erased" state in which their floating gate FG is at the same time. depleted state. Such a state is undesirable because it can generate read errors. The table RD1 in Appendix 1 indicates, in connection with FIG. 4, voltage values applied to the memory cells during the reading of the memory cell C11. Thus, during the reading of the memory cell C1, the common selection gate SGC of the two selection transistors ST11 and ST12 receives the read selection voltage Von. Transistors ST11, ST12 are therefore on. A current (represented by arrows in FIG. 4) flows in the channel region CH1 of the transistor FGT11 and in the channel region CH2 of the transistor ST11. This current is representative of the threshold voltage of the transistor FGT11 which is itself representative of a state programmed or erased from the transistor, which depends on a quantity of electric charges stored in its floating gate FG. This current is sensed by a sense amplifier not shown in FIG. 4, which provides a bit data stored by the memory cell C11. Thus, the selection transistor ST12 of the neighboring memory cell C12 is also put in the on state, and its channel CH2 is conducting. If the transistor FGT12 is in an over-erased state, it may also be passing. As a result, the memory cell Cl 1 will be seen to be reading and thus erased, even if it is locked (programmed). To avoid this phenomenon, the voltage CGV applied to the control gate of the transistor FGT12 can be set to a inhibition voltage Vinh which forces the transistor FGT12 in the off state and thus prevents it from driving even if it is in the over-erased state. In the table RD1, this voltage is chosen equal to -2 V which is lower than the threshold voltage of the floating gate transistors in the erased state. However, the generation of such a negative voltage causes an increase in the power consumption of a memory read operation, and requires a more complex CGV gate voltage control circuit. In a Flash-type memory, it is known to carry out a so-called "soft programming" programming operation following an erase operation, to increase the threshold voltages of the erased memory cells and thus prevent certain memory cells from being in the over-erased state. However, this solution necessarily increases the power consumption of the memory and the duration of the erase operations. FIG. 5 represents a pair of twin memory cells C1, C12, such as that described above with reference to FIG. 2. The table PG2 in Annex 1 described in connection with FIG. 5, voltage values applied to the memory cells C11. , C12, during the programming of the memory cell C11. The column "Ref." describes the reference assigned to each voltage value and the column "Ex." describes examples of voltage values. According to one embodiment, soft programming is applied to the memory cell C12 during a programming operation of the twin memory cell C11 of the pair of memory cells C11, C12. This soft programming is performed by submitting the state control gate CG of the memory cell C12 to a positive Vsp voltage lower than the programming voltage applied to the state control gate CG of the memory cell C11. The voltage Vsp is set to a value sufficient to turn on the channel CH1 of the transistor FGT12 and to establish an electric field capable of transferring a few electric charges into the floating gate FG of this transistor (the selection transistor ST12 being conducting just like the transistor ST11 ). However, the amount of electric charges transferred into the floating gate is insufficient to pass the memory cell C12 to the programmed state. The current 12 passing through the channels CH1, CH2 of the transistors FGT12, ST12 of the memory cell C12 during a conventional programming of the twin memory cell C11 (FIG. 3) is therefore used in FIG. 5 to carry out a soft programming of the C12 cell. Table RD2 in Appendix 1 describes in connection with FIG. 6 the voltage values applied to the memory cells during the reading of the memory cell C11. During the reading of the memory cell C11, the gates of the two selection transistors ST11 and ST12 receive the read selection voltage Von. Transistors ST11, ST12 are therefore on. A current 13 (represented by arrows in FIG. 5) flows in the channel region CH1 of the transistor FGT11 and in the channel region CH2 of the transistor ST11. Thus, the selection transistor ST12 of the neighboring memory cell C12 is put in the on state. According to one embodiment, the voltage CGV applied to the control gate of the transistor FGT12 is not fixed to the inhibition voltage Vinh, but to the voltage Vnr which is for example equal to the voltage GND. At this voltage value, the transistor FGT12 can only be on if it is in an "over-erased" state. However, if the memory cell C11 has been programmed, the memory cell C12 has been soft-programmed, and therefore can not be over-erased, and if the memory cell C11 is in the erased or over-erased state, the cell C12 memory is too. At the voltages Vrd and Vnr, the transistors FGT11, FGT12 of the cells C11, C12 are both blocked or passers-by. As a result, the reading of the cell C11 can not be disturbed by the possibly over-erased state of the twin cell C12.
[0009] The table ER2 in Appendix 1 indicates, in connection with FIG. 7, voltage values applied to the twin memory cells C11, C12 during an erasure operation thereof. According to one embodiment, the state control gates CG of the two twin memory cells receive the voltage Ver (= -10 V in the example of FIG. 7 and table ER2). The two memory cells C11, C12 are thus erased at the same time. Note that such an erasure operation is performed systematically before a programming operation of one or both twin memory cells C11, C12.
[0010] FIG. 8 shows distribution curves CV1, CV2, CV3 of the number N of memory cells of a memory as a function of a threshold voltage Vt of their respective floating gate transistors. Curves CV1, CV2, CV3 have the form of Gaussian. The CV1 curve centered on about -0.5 V, corresponds to the memory cells having undergone an erase operation. The CV2 curve centered on approximately 1 V corresponds to the memory cells which have been soft-programmed. Curve CV3 centered on about 5 V, corresponds to the memory cells in the programmed state. If the voltage Vnr is applied substantially equal to the ground voltage GND, to the selection control gates SCG of the memory memory twin cells of memory cells to be read, the memory cells having negative Vt threshold voltages, that is, that is, over-erased (CV1 curve), are busy. As a result, the read memory cells (C11) that are binocular of such memory cells (C12) are considered memory cells in the erased state. The soft programming which is performed on a memory cell (C12) during the programming of the twin memory cell (C11) makes it possible to shift the curve CV1 so as to obtain the curve CV2. As illustrated in FIG. 8, this offset is made in such a way that no memory cell of the memory considered, even those which were in the over-erased state, has a threshold voltage Vt lower than the voltage Vnr. , while avoiding that memory cells having been soft-programmed have a threshold voltage greater than the reading voltage Vrd (= 2 V in the example of table RD2 and of FIG. 8). The soft programming thus performed is performed only on the memory cells associated with a twin memory cell to be programmed, and simultaneously with the programming of the latter. This results in no penalty for the time required for erasure and programming operations, and a limited increase in power consumption since this is only due to soft programming which concerns only the memory cells of the memory cells. to be programmed and exploit current present when programming the twin cell. On the other hand, the fact of no longer having to generate the Vinh inhibition negative voltage makes it possible to reduce the electrical consumption of the reading operations. Compared to soft programming performed conventionally as a result of memory cell erasure, soft programming of pairs of memory cells to remain in the erased state is saved. It may be noted that the reading of a memory cell belonging to a pair of erased memory cells is not disturbed by the presence in this pair of a memory cell in the over-erased state. Indeed, if the read memory cell is in the over-erased state, it will be conductive to the reading voltage Vrd and thus seen as an erased cell. If the twin memory cell of the read memory cell is in the over-erased state, the two memory cells of the pair will be conducting, respectively at read voltages Vrd and Vnr. The read memory cell will therefore be considered in the erased state. FIG. 9 represents an erasable memory MEM1 per page comprising a memory plane made in a PW box. The memory array comprises M x N memory cells forming pairs of memory cells C11, C12, each memory cell C11, C12 comprising a charge accumulation transistor FGT11, FGT12 in series with a selection transistor ST11, ST12. The selection transistors ST11, ST12 of each pair share a common selection gate SGC. It should be noted that the two transistors ST11, ST12 with common gate of each pair of memory cells MEM1 may be replaced by the single selection transistor ST3 (FIG. 2). The memory MEM1 comprises M pages P each comprising a row of N memory cells, and a CGL grid control line. FIG. 9 shows two first pages P <0>, P <1> of ranks 0 and 1, and two pages P , P of ranks i and i + 1. The memory also comprises N 3021806 bit lines BL <j, k>, each being connected to a memory cell of the same rank in each page. The bit lines BL <j, k> can be grouped into word columns k of m + 1 bit lines, j being between 0 and m. Figure 9 shows the bit lines of two word columns k and k + 1. Each bit line BL <j, k> is connected to the drain regions n1 of the floating gate transistors FGT of memory cells of the same rank j, k. Each CGL gate control line is connected to the state control gates CG of the transistors FGT11, FGT12 of memory cells of same rank i. The source regions n3 of the selection transistors ST11, ST12 are connected to the NISO layer surrounding the PW box. The memory MEM1 also comprises control lines WL <i, i + 1> of the selection transistors ST11, ST12, which are connected to the common selection gates SGC of the selection transistors of the memory cells of two twin pages P <O> - P <1>, P -P . Thus, each line of control WL <i, i + 1> of rank i, i + 1 is associated with the two pages P , P binoculars of ranks i and i + 1 and controls the transistors selection ST11, ST12 of the memory cells of these two twin pages. The voltages applied to the various control lines BL <j, k>, CGL , WL <i, i + 1> of the memory array are provided by memory devices according to an address of a page to delete or a group of memory cells to read or program. These organs comprise: a CDEC column decoder, which connects the multiplexer MUX to the different bit lines. PGSW switches which apply to the different bit lines BL <j, k> connected to the memory cells of a word to be programmed B0-Bm, via the multiplexer MUX, the appropriate voltages BLV <j, k> during programming of the memory cells, - a word line pilot circuit WLDC which applies to the different word lines WL <i, i + 1> the voltages SV <i, i + 1> intended for the common selection gates 30 of the selection transistors ST11 , ST12, and which applies to the different gate control lines CGL the gate control voltages CGV of the floating gate transistors FGT11, FGT12, - a source line switch SLS which applies the line voltage from SLV source to the NISO layer forming a source plane, - a PWS box switch which applies the substrate voltage VB to the PW box, - SA amplifiers ("Sense Amplifiers"), which apply to the different lines bit BL <j, k> via the multiplexer MUX the corresponding BLV <j, k> voltages 5 during reading of memory cells, and provide the bits B0-Bm of a binary word read in the memory, and these members are configured to supply the voltages described in the table PG2, and possibly in tables RD2, ER2. In particular, during a programming operation, the word line pilot circuit WLDC supplies the programming voltage Vpg and the soft programming voltage Vsp appearing in the table PG2, to the state control gates CG of the memory cells of the pair of word lines WL <i, i + 1> including memory cells program. During an erase operation, the word line driver WLDC can supply the erase voltage Ver to the state control gates CG of the twin page memory cells P -P , causing the erasure of all the memory cells of these two twin pages. During a read operation, the read amplifiers SA provide the reading bias voltage BLV1 shown in the table RD2.
[0011] Thus, a programming operation of a word can be preceded by a reading operation of the pair of twin pages P -P in which the word to be written, word storage is located. read and write word for example in locks of bit lines BL <j, k> or in registers, and deletion of the twin pages P -P . The words of the twin pages are then sequentially programmed. The actual programming operation of the memory cells of a word is performed in two steps. In a first step, the programming voltage Vpg is applied to the gate control line CGL and simultaneously, the soft programming voltage Vsp is applied to the gate control line CGL . . In parallel, the bit lines BL <j, k> of the memory cells to be programmed with the word are subjected to the voltage BLV2, while the other bit lines remain at the voltage GND. In a second step, the programming voltage Vpg is applied to the gate control line CGL , and simultaneously, the soft programming voltage Vsp is applied to the gate control line CGL . In parallel, the 17 bit lines BL <j, k> of the memory cells to be programmed on the page PG are subjected to the voltage BLV2, while the other bit lines remain at the voltage GND. It should be noted that the application of soft programming to an already programmed memory cell or the application of programming to a memory cell having already undergone soft programming, does not significantly modify the threshold voltage of the transistor floating gate of this memory cell with respect to a memory cell which has only undergone programming.
[0012] According to one embodiment, each programming step of a word is subject to verification operations. These verification operations include a check operation of the depleted state of the memory cells to be programmed, and a verification operation of the programmed state of the memory cells that have undergone this operation. The depleted state check can be performed by applying the voltage Vnr (= GND in the example of table RD2) to the gate control line CGL or CGL of the memory cells to be checked. and performing a read operation at this voltage. The checking of the programming state can be carried out by applying a certain voltage Vpc (FIG. 8) to the CGL gate control line or CGL of the memory cells to be checked and carrying out an operation. reading at voltage Vpc. The voltage Vpc may be chosen greater than the reading voltage Vrd and lower than the threshold voltage of the floating gate transistors in the programmed state. According to one embodiment, programming with verification of a memory cell is performed by performing steps S01 to S09 shown in Fig. 10. At step 501, a simple programming operation is applied to the memory cell to be programmed. , without applying soft programming to the twin memory cell. The twin memory cell can thus receive on its control gate CG the voltage Vnp, for example equal to the ground voltage. In step S02, a check operation of the depleted state of the memory cell to be programmed and the twin memory cell is performed. In step S03, if one of the twin memory cells is in the depleted state, the steps S04, S05 and S06 are executed, otherwise steps S07 and S08 are executed. In step SO4, a programming operation is applied to the memory cell to be programmed and a soft programming operation is applied to the twin memory cell. Step S05 consists of a new operation for checking the depleted state of the pair of memory cells. In step S06, if either of the twin memory cells is in the depleted state, steps S04, S05 and S06 are executed again, otherwise steps S07 and S08 are executed. In step S07, a program status check operation is applied to the memory cell to be programmed. In step S08, if the memory cell to be programmed is in the programmed state, programming of the memory cell is completed, otherwise steps S09, S07 and S08 are executed. In step S09, a simple programming operation is applied to the memory cell to be programmed. It will be apparent to those skilled in the art that the present invention is capable of various alternative embodiments and various applications. In particular, the invention does not necessarily apply to a memory 15 such as that shown in FIG. 9, but can be applied to any circuit comprising at least one pair of twin memory cells, such as the pair of memory cells. FIG. 1 and 2. The present invention does not necessarily apply to an erasable memory per page, but can be applied to a multi-page sectorally erasable memory per word. or by bit. The programming operation including soft programming (table PG2) can be implemented in a memory in which read operations in accordance with table RD1 and erasure in accordance with table ER1 are implemented. Similarly, only one of the erasure and read operations in accordance with Tables ER2 and RD2 may be implemented in a memory implementing programming associated with soft programming (Table PG2) to program a memory cell of a pair of twin memory cells. On the other hand, the soft programming and programming voltages are not necessarily applied simultaneously to the two memory cells of a pair of twin memory cells respectively. The present invention also applies to a pair of twin memory cells sharing a single selection transistor. FIG. 11 is a circuit diagram of such a pair of memory cells C21, C22. The pair of memory cells C21, C22 differs from the pair of memory cells C11, C12 in that the selection transistors ST11, ST12 are replaced by a single transistor ST3 which they share.
[0013] Annex 1 forming an integral part of the description Examples of voltage values during the reading of a memory cell RD1 Ref. Ex. Reading of the memory cell C11 (figure 5) BLV BLV1 1V Bias bias of the bit line CGV1 Vrd 2V Reading voltage of the transistor FGT11 CGV2 Vinh -2V Inhibit voltage of the transistor FGT12 VB VB1 GND Polarization voltage of the box PW SV Von 2V Reading selection voltage of transistors ST11, ST12 SLV VI1 GND Polarization voltage of source line NISO RD2 Ref. Ex. Reading memory cell C11 (Figure 7) BLV BLV1 1V Bias bias voltage CGV1 Vrd 2V Transistor voltage of FGT11 transistor CGV2 Vnr GND Transistor voltage of transistor FGT12 VB VB1 GND PW bias voltage PW SV Von 2V Reading voltage of transistors ST11, ST12 SLV VI1 GND Voltage bias of source line NISO 3021806 21 Examples of voltage values during deletion of a memory cell ER1 Ref. Ex. Clear memory cell C11 BLV BLV2 GND Bias line voltage CGV1 Ver -10V Clear transistor FGT1 voltage 1 CGV2 Vner 2.5V Transistor FGT12 VB VB2 non-erase voltage 5V Polarization voltage PW SV SV2 5V Transistor voltage of the transistors ST1 1, ST12 SLV VI2 5V Polarization voltage of the NISO ER2 source line Ref. Ex. Clearing memory cells C11, C12 (Figure 8) BLV BLV2 GND Bias line voltage CGV1 Ver -10V Clearing voltage of transistor FGT1 1 CGV2 Ver -10V Clearing voltage of transistor FGT12 VB VB2 5V PW SV2 voltage bias voltage 5V Transistor voltage of transistors ST1 1, ST12 SLV VI2 5V NISO source line bias voltage 3021806 22 Examples of voltage values during programming of a PG1 memory cell Ref. Ex. Programming memory cell C11 (Figure 4) BLV2 BLV2 4V Bias line bias voltage CGV1 Vpg 10V FGT11 transistor programming voltage CGV2 Vnp GND Transistor FGT12 VB VB3 GND non-programming voltage Polarization bias voltage box PW SV Von 2V Transistor voltage of transistors ST11, ST12 SLV VI3 GND Polarization voltage of source line NISO PG2 Ref. Ex. Programming memory cell C11 (Figure 6) BLV3 BLV3 4V Bias line bias voltage CGV1 Vpg 10V FGT11 transistor programming voltage CGV2 Vsp 5V Soft transistor programming voltage FGT12 VB VB3 GND Bias bias voltage PW SV Von 2V Transistor Voltage ST11, ST12 SLV VI3 GND Polarization Voltage of NISO Source Line

权利要求:
Claims (15)
[0001]
REVENDICATIONS1. A method of controlling a nonvolatile memory on a semiconductor substrate (PW), comprising: at least one bit line (BL), at least two gate control lines (CGL , CGL ), at least one word line (WL <i, i + 1>), and at least one pair of twin memory cells (C11, C12, C21, C22), including a first memory cell comprising a first floating gate transistor (FGT11) having a control gate (CG) connected to a first gate control line (CGL ), a first conduction terminal connected to the bit line and a second conduction terminal connected to a source line via a first selection transistor (ST11, ST3) having a selection control gate (SGC) connected to the word line, and a second memory cell having a second floating gate transistor (FGT12) having a control gate connected to the second gate control line (CGL ), a first lead terminal connected to the bit line and a second conduction terminal connected to the source line via a second selection transistor (ST12, ST3) sharing with the first selection transistor the selection control gate, characterized in that it comprises the steps of: programming the first memory cell (C11, C21) by injecting hot electrons, via a programming current (11) passing through the first memory cell, applying a first positive voltage (BLV3) to the bit line (BL) and a second positive voltage (Vpg) to the first gate control line (CGL ), and during the programming of the first memory cell, apply to the second grid control line (CGL ) a third positive voltage (Vsp) able to pass a programming current (12) in the second memory cell (C12, C22), without passing the second memory cell in a progress state Amme.
[0002]
2. Method according to claim 1, wherein the third voltage (Vsp) is chosen so as to ensure soft programming of the second memory cell (C12, C22), so that the second memory cell can not present a voltage. negative threshold regardless of its programmed or erased state. 5
[0003]
The method of claim 1 or 2, comprising steps of reading a memory cell (C11, C12, C21, C22) of the pair of memory cells, comprising: applying a positive read voltage (Vrd) to the control gate of the floating gate transistor of the memory cell to be read, and apply zero voltage (Vnr) to the control gate of the floating gate transistor of the twin memory cell.
[0004]
4. Method according to one of claims 1 to 3, comprising an erasing step of simultaneously applying an erase voltage (Ver) to the control gates (CG) of the floating gate transistors (FGT11, FGT12) of first and second memory cells (C11, C12, C21, C22).
[0005]
5. Method according to one of claims 1 to 4, wherein the programming operation of the first memory cell (C11) comprises steps of checking the depleted state of the pair of memory cells, and of performing programming of the first memory cell and soft programming of the second memory cell as long as one or the other of the first and second memory cells is in the depleted state, followed by verification steps of the first memory cell; programmed state of the first memory cell, and programming of the first memory cell as long as it is not in the programmed state.
[0006]
A non-volatile memory on a semiconductor substrate (PW), comprising: at least one bit line (BL), at least two gate control lines (CGL , CGL ), at minus one word line (WL <i, i + 1>), at least one pair of twin memory cells (C11, C12, C21, C22), having a first memory cell including a first floating gate transistor (FGT11) ) having a control gate (CG) connected to a first gate control line (CGL ), a first conduction terminal connected to the bit line and a second conduction terminal connected to a source line through the intermediate of a first selection transistor (ST11, ST3) having a selection control gate (SGC) connected to the word line, and a second memory cell having a second floating gate transistor (FGT12) having a gate control connected to the second gate control line (CGL ), a first connected conduction terminal the bit line and a second conduction terminal connected to the source line 10 via a second selection transistor (ST12, ST3) sharing with the first selection transistor the selection control gate, and means for programming the first memory cell independently of the second memory cell and vice versa, characterized in that the memory is configured to: program the first memory cell (C11, C21) by hot electron injection, via a programming current (11) passing through the first memory cell, applying a first positive voltage (BLV3) to the bit line (BL) and a second positive voltage (Vpg) to the first gate control line (CGL ), and during the programming of the first memory cell, apply to the second gate control line (CGL ) a positive third voltage (Vsp) capable of passing a program current. in the second memory cell (C12, C22) without passing the second memory cell 25 into a programmed state.
[0007]
The memory of claim 6, wherein the third voltage (Vsp) is selected to provide soft programming of the second memory cell (C12, C22), so that the second memory cell can not exhibit a voltage of Negative threshold whatever its state programmed or erased.
[0008]
Memory according to claim 6 or 7, comprising a word line decoder (WLDC) connected to the word line (WL <i, i + 1>) and to the gate control lines (CGL , CGL ), the decoder being configured for, during reading of a memory cell of the pair of twin memory cells (C11, C12, C21, C22), applying a positive read voltage (Vrd) to the control gate (CG) of the floating gate transistor (FGT11, FT12) of the memory cell to be read, and applying a voltage (Vnr) of zero to the control gate of the floating gate transistor of the twin memory cell .
[0009]
9. Memory according to one of claims 6 to 8, wherein the selection control gate (SCG) is a buried vertical gate having 10 for the first selection transistor (ST11) a vertical channel region (CH2) s' extending facing a first face of the buried vertical control gate, and for the second selection transistor (ST12) a vertical channel region (CH2) extending opposite a second face of the control gate buried vertical, and in front of the channel region of the first selection transistor.
[0010]
10. Memory according to one of claims 6 to 9, wherein the memory cells (C21, C22) of the pair of twin memory cells share a single selection transistor (ST3). 20
[0011]
The memory according to one of claims 6 to 10, wherein the pair of memory cells (C11, C12) comprises: a first doped region (n2) extending along a first upper edge of the buried gate ( SGC), forming a drain region of the select transistor (ST11) and a source region of the floating gate transistor (FGT11), a first memory cell (C11) of the pair of memory cells, a second doped region (n2) extending along a second upper edge of the buried gate opposite the first upper edge, forming a drain region of the selection transistor (ST12) and a source region of the floating gate transistor (FGT12) , a second memory cell (C12) of the pair of memory cells, and a third doped region (NISO, n3) extending along two opposite lower edges of the buried gate, forming a common source region 3021806 of the selection transistor (ST11) of the first memory cell and the selection transistor (ST12) of the second memory cell, each selection transistor (ST11, ST12) of the pair of memory cells having a vertical channel region (CH2) extending from a respective side buried gate, between the first or the second doped region and the third doped region.
[0012]
Memory according to one of claims 6 to 11, comprising a word line decoder (WLDC) connected to the word line (WL <i, i + 1>) and the gate control lines (CGL , CGL ), the decoder being configured for, during memory cell erasure, applying an erase voltage (Ver) simultaneously to the first and second gate control lines (CGL , CGL ). 15
[0013]
13. Memory according to one of claims 6 to 12, configured for, during the programming operation of the first memory cell (C11, C21): check the depleted state of the pair of memory cells (C11, C12, C21) , C22), and program the first memory cell and simultaneously apply soft programming to the second memory cell (C12, C21), as long as either one of the first and second memory cells is in the depleted state, and verify the programmed state of the first memory cell, and program the first memory cell as long as it is not in the programmed state.
[0014]
Memory according to one of claims 6 to 13, comprising a row of twin memory cell pairs connected to the word line (WL <i, i + 1>) and to the grid control lines (CGL , CGL ), the memory being configured to program a word formed by a plurality of memory cells in the row, connected to one of the two grid control lines, and for, during word programming: perform a read operation of the row of pairs of twin memory cells (C11, C12, C21, C22) and storage of words read, perform an operation of erasing the row of pairs of read memory cells, perform a word programming memory cells of the row of memory cell pairs, comprising programming the first memory cell (C11, C21) of the memory cell pairs of the row, according to the stored words and possibly the word to be written, and simultaneously performed and soft programming second memory cells (C12, C22) of the first programmed memory cells, and performing a second programming operation of the second memory cell of the memory cell pairs of the array, based on the stored words and optionally the word to write, and simultaneously perform soft programming of the first twin memory cells of the second programmed memory cells.
[0015]
15

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优先权:

申请号 | 申请日 | 专利标题

FR1454839A|FR3021806B1|2014-05-28|2014-05-28|METHOD FOR PROGRAMMING NONVOLATILE MEMORY CELL COMPRISING A SHARED SELECTION TRANSISTOR GRID|FR1454839A| FR3021806B1|2014-05-28|2014-05-28|METHOD FOR PROGRAMMING NONVOLATILE MEMORY CELL COMPRISING A SHARED SELECTION TRANSISTOR GRID|

CN201510247063.1A| CN105280225B|2014-05-28|2015-05-14|The method that the Nonvolatile memery unit for including shared selection transistor grid is programmed|

CN201520312733.9U| CN204904840U|2014-05-28|2015-05-14|Nonvolatile memory unit of transistor gate is selected including sharing|

US14/719,913| US9443598B2|2014-05-28|2015-05-22|Method for programming a non-volatile memory cell comprising a shared select transistor gate|

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